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PAC7301/PAC7302
PAC7302 VGA Output PC Camera SOC with Audio PAC7301 VGA Output PC Camera SOC without Audio General Description
The PAC7301/PAC7302 is a VGA output PC Camera SOC with embedded CMOS image sensor and USB 1.1 interface. It embedded a JPEG image compression engine and an image signal processor (ISP). The JPEG decoder and auto exposure control are performed by software in PC side. The PAC7301/PAC7302 can achieve a compact module size by using it's 1/6" optical size which can easily be embedded in LCD monitors and notebooks. The chip provides IO-trapping pins with internal pull-up resistors. Hence it is flexible for customers to set PID on module PCB. It supports an interface connect to a serial-EEPROM. When the EEPROM function is enabled, the internal control register setting will be auto loaded to the external EEPROM. This allows customization of VID, PID, product string...etc. PAC7301/PAC7302 also provide a high quality audio ADC function for sound recording. The audio-in function complies with USB audio device class 1.0. The PAC7301/PAC7302 is powered by 5V and in PLCC/CSP/LGA package
1. Feature
Embedded CMOS image sensor with VGA output Frame rate up to 30fps@VGA for PC mode video Embedded PixArt 3rd generation ISP and JPEG compression engine AEC/AGC/AWB automatic On chip 10bit ADC for image date converter External 12MHz crystal input 5 IO-trapping pins to set USB PID Support video data transfer through USB isochronous transfer Snapshot and LED control function Built-in EEPROM controller for customized VID, PID etc USB1.1 compliance and support USB suspend mode Embedded audio function (PAC7301/PAC7302) -- 10bits ADC for audio recording through microphone, -- sampling rate @ 16K/48KHz, 16bits PCM format -- USB audio device class 1.0 compatible On chip regulator(LDO) for internal use 5V single power supply
2. Ordering Information
Order number PAC7302PE PAC7302PM PAC7301/PAC73 02LT PAC7302LG Package Type 48-pin PLCC 40-pin PLCC 35-pin CSP 30-pin LGA Package Size(mm) 11.43 x 11.43 9.0x9.0 3.95x3.95 3.95x3.95
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3. Pin Assignment 3.1 PLCC Package(11.43X11.43)
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name MIC_N VSSA_AUDIO VDDADC33 GPI3 GPO1 NC NC TEST2 RESET# GPI1 VSSQ EPR_DO/TR3 EPR_DI/TR0 EPR_SK/TR2 EPR_CS/TR1 LED GPI2 NC NC EPR_EN AUD_EnH VSSQ VDDD VDDMD5 VDDQ OSC_OUT OSC_IN DN DP NC NC GPO2 KEY# VSSA VSSAY VDDA VDDAYM VDDAY VDDA33 VDDMA5 Type IN GND BYPASS IN OUT IN IN IN GND IN OUT OUT OUT OUT IN IN IN GND BYPASS PWR BYPASS OUT IN I/O I/O OUT IN GND GND BYPASS BYPASS BYPASS BYPASS PWR IN PWR Description Microphone negative input Audio analog circuit GND Audio ADC power ,3.3V General purpose input pin General purpose output pin No Connection No Connection Test pin. Connect to GND in normal operation mode, internal pull-down 100Kohm Chip power up reset General purpose input pin Digital Ground for I/O and PHY, digital core. Data out of EEPROM (IO trap pin for PID3, internal pull-up 100Kohm) Data input of EEPROM (IO trap pin for PID0, internal pull-up 100Kohm) Serial clock of EEPROM (IO trap pin for PID2, internal pull-up 100Kohm) Chip select of EEPROM (IO trap pin for PID1, internal pull-up 100Kohm) LED driver General purpose input pin No Connection No Connection EEPROM enable pin active high Audio enable pin, High active, internal pull-up 100Kohm Digital Ground for I/O and PHY, digital core. Logic power for digital circuit, 1.8V 5V power for digital circuit Power for I/O and PHY, 3.3V Crystal output Crystal input DN for USB1.1 PHY DP for USB1.1 PHY No Connection No Connection General purpose output pin, internal pull-up 100Kohm, reserve VID Snapshot control signal (Active Low, internal pull-up 100Kohm) Analog ground Sensor ground Analog power for Video PGA/ADC 2.5V Analog power for sensor CDS 2.5V Analog power for sensor array 2.5V Analog power output 3.3V(for 2.5 regulator use) 5V power for video analog circuit Test pin. Connect to GND in normal operation mode, internal pull-down 100Kohm No Connection No Connection 5V power for analog audio circuit
41 TEST1 42 NC 43 NC VDDMA5_AU 44 D 45 VDDPGA33 46 VCOM
BYPASS Analog power output for audio PGA 3.3V BYPASS Microphone common mode voltage reference(audio power) 2
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47 VDDMIC28 48 MIC_P BYPASS Analog MIC reference audio power 2.8V IN Microphone positive input
3.2 PLCC Package(9X9)
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name MIC_N VSSA_AUDIO VDDADC33 GPI3 GPO1 TEST2 RESET# GPI1 VSSQ EPR_DO/TR3 EPR_DI/TR0 EPR_SK/TR2 EPR_CS/TR1 LED GPI2 EPR_EN AUD_EnH VSSQ VDDD VDDMD5 VDDQ OSC_OUT OSC_IN DN DP GPO2 KEY# VSSA VSSAY VDDA VDDAYM VDDAY VDDA33 VDDMA5 Type IN GND BYPASS IN OUT IN IN IN GND IN OUT OUT OUT OUT IN IN IN GND BYPASS PWR BYPASS OUT IN I/O I/O OUT IN GND GND BYPASS BYPASS BYPASS BYPASS PWR IN PWR BYPASS BYPASS BYPASS IN Description Microphone negative input Audio analog circuit GND Audio ADC power ,3.3V General purpose input pin General purpose output pin Test pin. Connect to GND in normal operation mode, internal pull-down 100Kohm Chip power up reset General purpose input pin Digital Ground for I/O and PHY, digital core. Data out of EEPROM (IO trap pin for PID3, internal pull-up 100Kohm) Data input of EEPROM (IO trap pin for PID0, internal pull-up 100Kohm) Serial clock of EEPROM (IO trap pin for PID2, internal pull-up 100Kohm) Chip select of EEPROM (IO trap pin for PID1, internal pull-up 100Kohm) LED driver General purpose input pin EEPROM enable pin active high Audio enable pin, High active, internal pull-up 100Kohm Digital Ground for I/O and PHY, digital core. Logic power for digital circuit, 1.8V 5V power for digital circuit Power for I/O and PHY, 3.3V Crystal output Crystal input DN for USB1.1 PHY DP for USB1.1 PHY General purpose output pin, internal pull-up 100Kohm, reserve VID Snapshot control signal (Active Low, internal pull-up 100Kohm) Analog ground Sensor ground Analog power for Video PGA/ADC 2.5V Analog power for sensor CDS 2.5V Analog power for sensor array 2.5V Analog power output 3.3V(for 2.5 regulator use) 5V power for video analog circuit Test pin. Connect to GND in normal operation mode, internal pull-down 100Kohm 5V power for analog audio circuit Analog power output for audio PGA 3.3V Microphone common mode voltage reference(audio power) Analog MIC reference audio power 2.8V Microphone positive input
35 TEST1 36 37 38 39 40 VDDMA5_AU D VDDPGA33 VCOM VDDMIC28 MIC_P
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3.3 CSP Package
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Name GPO1 VDDADC33 MIC_N VDDMIC28 VDDPGA33 VDDMA5_AU D RESET# GPI3 VSSA_AUDIO MIC_P VDDMA5 VDDA33 VSSQ GPI1 VCOM VDDAY VDDAYM EPR_DI/TR0 EPR_SK/TR2 EPR_DO/TR3 VDDA KEY# VSSAY EPR_CS/TR1 LED VDDD VDDQ OSC_IN VSSA EPR_EN VSSQ VDDMD5 OSC_OUT DN DP Type OUT BYPASS IN BYPASS BYPASS PWR IN IN GND IN PWR BYPASS GND IN BYPASS BYPASS BYPASS OUT OUT IN BYPASS IN GND OUT OUT BYPASS BYPASS IN GND IN GND PWR OUT I/O I/O Description General purpose output pin Audio ADC power ,3.3V Microphone negative input Analog MIC reference audio power 2.8V Analog power output for audio PGA 3.3V 5V power for analog audio circuit Chip power up reset General purpose input pin Audio analog circuit GND Microphone positive input 5V power for video analog circuit Analog power output 3.3V(for 2.5 regulator use) Digital Ground for I/O and PHY, digital core. General purpose input pin Microphone common mode voltage reference(audio power) Analog power for sensor array 2.5V Analog power for sensor CDS 2.5V Data input of EEPROM (IO trap pin for PID0, internal pull-up 100Kohm) Serial clock of EEPROM (IO trap pin for PID2, internal pull-up 100Kohm) Data out of EEPROM (IO trap pin for PID3, internal pull-up 100Kohm) Analog power for Video PGA/ADC 2.5V Snapshot control signal (Active Low, internal pull-up 100Kohm) Sensor ground Chip select of EEPROM (IO trap pin for PID1, internal pull-up 100Kohm) LED driver Logic power for digital circuit, 1.8V Power for I/O and PHY, 3.3V Crystal input Analog ground EEPROM enable pin active high Ground for I/O and PHY 5V power for digital circuit Crystal output DN for USB1.1 PHY DP for USB1.1 PHY
3.4 LGA Package
Pin# 1 2 3 4 5 6 7 8 Name GPO1 VDDADC33 VSSA_AUDIO MIC_N MIC_P VDDMIC28 VCOM VDDPGA33 Type OUT BYPASS GND IN IN BYPASS BYPASS BYPASS Description General purpose output pin Audio ADC power ,3.3V Audio analog circuit GND Microphone negative input Microphone positive input Analog MIC reference audio power 2.8V Microphone common mode voltage reference(audio power) Analog power output for audio PGA 3.3V 4
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9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VDDMA5 VDDA33 VDDAY VDDAYM VDDA VSSA KEY# DP DN OSC_IN OSC_OUT VDDQ VDDMD5 VDDD VSSQ EPR_EN LED NC NC VSSQ GPI1 RESET# PWR BYPASS BYPASS BYPASS BYPASS GND IN I/O I/O IN OUT BYPASS PWR BYPASS GND IN OUT GND IN IN 5V power for video analog circuit Analog power output 3.3V(for 2.5 regulator use) Analog power for sensor array 2.5V Analog power for sensor CDS 2.5V Analog power for Video PGA/ADC 2.5V Analog ground Snapshot control signal (Active Low, internal pull-up 100Kohm) DP for USB1.1 PHY DN for USB1.1 PHY Crystal input Crystal output Power for I/O and PHY, 3.3V 5V power for digital circuit Logic power for digital circuit, 1.8V Digital Ground for I/O and PHY, digital core. EEPROM enable pin active high LED driver No Connection No Connection Digital Ground for I/O and PHY, digital core. General purpose input pin Chip power up reset
4. Block Diagram
PAC7301/PAC7302 is a USB PC Camera SOC with enhanced image quality and sensitivity, internal regulators, JPEG image compression, image processing schemed, control registers, on-chip SRAM for image data buffer and USB controller. All register parameters are set by USB interface. And the JPEG compressed image data is transmitted by USB 1.1 isochronous pipe.
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5. Function Description 5.1 Analog Data Path
The sensor array is covered by Bayer pattern color filters and micro lens. After a programmable exposure time, the image is sampled first with CDS (Correlated Double Sampling) block to improve S/N ration and reduce fixed pattern noise. Three analog gain stages are implemented before signal transferred by the 10bit ADC. The front gain stage (FG) can be programmed to fit the saturation level of sensor to the full-range input of ADC. The programmable color gain stage (CG) is used to balance the luminance response difference between B/G/R. The global gain stage (GG) is programmed to adapt the gain to the image luminance. The fine gained signal will be digitized by the on-chip 10bit ADC. After the image data has been digitized, further alteration to the signal can be applied before the data is output. The gain stage can be set by digital register, please refer to the following equation to get the mapping gain. Front Gain = 2 + (n/4), n = 0, 1, 2, ...7 Color Gain = (1 +m)/16, m= 0, 1, 2, ...31 Global Gain = (1 +q)/16, q = 0, 1, 2, ...31
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6. Specifications
Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings shown below invalidates all AC and DC electrical specifications and may result in permanent device damage.
Symbol TSTG VDD VIN VOUT ESD
Parameter Ambient storage temperature DC supply voltage DC input voltage DC output voltage ESD Rating, Human Body model
Min -25 -0.5 0.5 -0.5
Max 125 5.5 3.8 3.8 2
Unit C V V V kV
Notes
Recommend Operating Condition Symbol TA VDD FCLK Parameter Temperature Operation Range Stable Image Power supply voltage System clock frequency Min -10 0 4.5 Typ. 5.0 12.0 Max 70 50 5.5 Unit C C V MHz Notes
DC Electrical Characteristics (Typical values at 25C, VDD =5.0V, FCLK=12.0MHz) Symbol Type: PWR IDD IDD Operating Current Suspend Current 35 500 mA uA @30 frame/sec Parameter Min. Typ. Max. Unit Notes
Type: IN & I/O, Reset VIH VIL CIN ILKG Input voltage HIGH Input voltage LOW Input capacitor Input leakage current 2 0 VDDQ 0.8 10 1.0 V V pF uA
Type: OUT & I/O VOH VOL Output voltage HIGH Output voltage LOW Vddq-0.2 0.2 V V CL= 10pf, RL=1.2k CL= 10pf, RL=1.2k
Sensor Characteristics (Light source: 3200K halogen lamp; 8bit resolutions) Symbol PRNU VSAT VDARK DSNU R G B Parameter Photo response non-uniformity Saturation output voltage Dark output voltage Dark signal non-uniformity Sensitivity (Red channel) Sensitivity (Green channel) Sensitivity (Blue channel) Min. Typ. 1.2 1 1.08m 0.001 1.19 1.2 0.85 Max. Unit % V V/sec V V/((uw/cm2)*sec) V/((uw/cm2)*sec) V/((uw/cm2)*sec) 7 Notes
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7. Package Information 7.1 .1 PAC7302PE(11.43X11.43) Pin Assignment and Optical Center Information
Note: Sensor Array Center = Package Center
--TOP VIEW--
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7.1.2 PAC7302PE(11.43X11.43) Package Outline Dimension
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7.1.3 PAC7302PE(11.43X11.43) Recommend PCB Layout
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PixArt Imaging Inc. PAC7301/PAC7302
7.2 PAC7302PM(9.0x9.0) Pin Assignment and Optical Center Information
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PixArt Imaging Inc. PAC7301/PAC7302
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7.3.1 CSP Pin Assignment and Optical Center Information
1962
1476
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7.3.2.CSP Package Ball Matrix Table
1 A GPO1(PIN 1) B RSTN(PIN 7) C VSSQ (PIN 13) D EPR_DI(PIN 18) E F 2
GPI3(PIN 8) GPI1(PIN14)
3
4
5
VDDMA5(PIN 11) VDDAY(PIN 16)
6
VDDA33(PIN 12) VDDAYM(PIN 17)
VDDADC33(PIN 2) MIC_N(PIN 3)
VDDMIC28(PIN 4) VDDPGA33(PIN 5) VDDMA5_AUDIO(PIN 6)
VSSA_AUDIO(PIN 9) MIC_P(PIN 10) VCOM(PIN 15)
EPR_SK (PIN 19)
EPR_DO (PIN 20) VDDD (PIN 26) VDDMD5 (PIN32)
VDDA (PIN 21) VDDQ (PIN 27)
KEY(PIN 22) OSC_IN(PIN 28)
VSSAY(PIN 23) VSSA(PIN 29) DP(PIN 35)
EPR_CS(PIN 24) LED(PIN 25) EPR_EN(PIN 30) VSSQ(PIN 31)
OSC_OUT(PIN 33) DN(PIN 34)
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7.3.3 PAC7302LT Recommend PCB Layout
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7.4.1 LGA Pin Assignment and Optical Center Information
1962
1476
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7.4.2.LGA Package Ball Matrix Table
F G H
NC(P26) LED(P25) EPR_EN(P24) VSSQ(P23) VDDD(P22) VDDMD5(P21) VDDQ(P20) OSC_OUT(P19) OSC_IN(P18) DN(P17)
VSSAY(P14) KEY(P15) DP(P16)
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7.4.3 PAC7302LG Recommend PCB Layout
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8. Reference Application Circuit 8.1 PLCC(11.43x11.43) Package (PAC7302PE)
VDDQ VDDA 0 R27 VDDAY VDDQ R1 R28 1k 100k 1 LED-0603 D1 VDD_5V 0 or 3.3uH VDDMA5_AUD R17 VDDMD5 VDDMA5 0 or 3.3uH R18 18 17 U2 0 or 3.3uH R19 19 20 21 22 VDDD 23 VDDMD5 24 10pF C3 Y1 R7 OSC_IN 10pF 1M C5 12MHz DN DP 28 29 30 27 VDDQ 25 OSC_OUT 26 R2 300k C1 1uF EPR_CS EPR_DO EPR_SK VDDMIC28 EPR_DI R23 0 C18 C21 + 1uF VDDA33 10uF_N.M. 0.1uF_N.M. VDDADC33 10uF + 2 C13 1uF VDDAY 16 15 14 13 12 11 10 9 RSTN 8 LED R22 0 7 R26 5.1k NC GPO1 GPI3 VDDADC33 VSSA_AUDIO MIC_N PAC7301/7302PE MIC_P VDDMIC28 VCOM VDDPGA33 VDDMA5_AUD VDDAYM VDDMA5 VDDA33 VDDAY VSSAY TEST1 NC NC 6 R29 0 5 R25 0 4 3 2 1 48 47 46 45 44 43 C22 C6 C7 0.1uF 10uF + C25 C27 U3 L1 VDDQ 1.5K R11 DP KEY L3 VDD_5V short VDD5V C23 0.1uF C19 + 10uF short R12 1 2 3 4 5 R13 R14 6 7 USBGND C29 R16 4.7nF/250V 10M HC1 HC2 CON1 MINI USB 5P USBGND HC4 HC3 9 8 R15 10K_N.M. EPR_DI 10K_N.M. EPR_DO 10K_N.M. EPR_SK 10K_N.M. EPR_CS Open Open Open Open Open Open Open Short . . . Short Open Open Open . . . Short Short Short Open Short Short Short Short 2620 2621 (Def ault) C17 C20 2628 C9 262E 262F + 1uF VDDQ 10uF_N.M. L4 VSSA 3.3uH VSSQ L2 3.3uH VSSA_Audio C8 1uF VDDD + 1uF VDDA 10uF_N.M. C24 0.1uF VDDMA5 10uF + MIC_N MIC_P VDDMIC28 VCOM VDDPGA33 VDDMA5_AUD R6 10k 2.2uF R5 C4 10k 2.2uF R8 2.2k C15 C16 0.1uF VDDMA5_AUD 10uF + VDDADC33 C2 X1 C10 C11 0.1uF_N.M. VDDMIC28 22uF + R3 2.2k + C32 22uF C30 C31 0.1uF_N.M. VDDPGA33 10uF + C26 C28 EPR_SK/TR2 GPI2 EPE_DI/TR0 EPR_DO/TR3 EPR_CS/TR1 TEST2 VSSQ GPI1 RSTN
NC
LED
NC EPR_EN AUD_EnH VSSQ VDDD VDDMD5 VDDQ OSC_OUT OSC_IN DN DP NC GPO2
NC
MICROPHONE
DN
DP
VSSQ
31
32
33
34
35
36
VDDA
VSSA
KEY
NC
VDDAYM37
VDDAY 38
VDDA33 39
VDDMA540
41
R9 R10 27 27
VDDA
KEY
42
PID IO_TRAP
R12 R13 R14 R15 PID
+5V + NC GND2
PAC7302 PID IO_TRAP
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+
C12 C14
0.1uF VDDMD5 10uF + 1uF VDDAY M
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PixArt Imaging Inc. PAC7301/PAC7302
8.2 PLCC (9.0x9.0) Package (PAC7302PM)
VDDQ VDDQ R1 R28 1k 100k VDD_5V 0 or 3.3uH VDDMA5_AUD R17 VDDMD5 VDDMA5 0 or 3.3uH R18 0 or 3.3uH R19 U2 R23 0 1 LED-0603 300k C1 1uF C10 C11 2 EPR_CS EPR_DO EPR_SK VDDMIC28 EPR_DI R22 0 0.1uF_N.M. VDDMIC28 22uF + D1 R2 R27 0 VDDA VDDAY RSTN LED C15 R26 5.1k C16 0.1uF VDDMA5_AUD 10uF +
15
14
13
12
11
10
9
8
7 RSTN
VSSQ
GPI2
GPI1
EPR_DO
EPR_CS
EPR_SK
EPE_DI
TEST2
LED
6
R29 0 GPO1 GPI3 VDDADC33 VSSA_AUDIO MIC_N 5 R25 0 4 3 2 1 40 39 38 37 36 MIC_N MIC_P VDDMIC28 VCOM VDDPGA33 VDDMA5_AUD R6 10k 2.2uF R5 C4 10k 2.2uF R8 2.2k VDDADC33 C2 X1 R3 2.2k + C32 22uF
C22 C24
0.1uF VDDMA5 10uF +
16 17 18 VDDD 19 VDDMD5 20 10pF C3 Y1 R7 OSC_IN 10pF 1M C5 12MHz DN DP 24 25 23 VDDQ 21 OSC_OUT 22
EPR_EN AUD_EnH VSSD VDDD VDDMD5 VDDQ OSC_OUT OSC_IN DN DP VDDAYM VDDMA5 VDDA33 VDDAY VSSAY PAC7302PM
C9
1uF
VDDAY M
MIC_P VDDMIC28 VCOM VDDPGA33 VDDMA5_AUD TEST1
MICROPHONE
DN
DP
VDDA
GPO2
VSSA
VSSQ
KEY
26
27
28
29
30
VDDAYM31
VDDAY 32
VDDA33 33
VDDMA534
R9 R10 VDDA 27 27 KEY
35
C6 C7
0.1uF 10uF +
U3 L1 VDDQ 1.5K R11 DP KEY L4 VDD_5V short short R12 1 2 3 4 5 C23 0.1uF C19 + 10uF R13 R14 6 7 USBGND C29 R16 4.7nF/250V 10M HC1 HC2 CON1 MINI USB 5P USBGND HC4 HC3 9 8 R15 10K_N.M. EPR_DI 10K_N.M. EPR_DO 10K_N.M. EPR_SK 10K_N.M. EPR_CS Open Open Open Open Open Open Open Short . . . Short Open Open Open . . . Short Short Short Open Short Short Short Short 2620 2621 C17 2628 C20 + 262E 262F C25 C27 + 1uF VDDA 10uF_N.M. 10uF_N.M. (Def ault) C14 10uF + C8 1uF VDDD L5 VSSA 3.3uH VSSQ L2 3.3uH C31 10uF +
PID IO_TRAP
R12 R13 R14 R15 PID C12 0.1uF VDDMD5
+5V + NC GND2
PAC7302 PID IO_TRAP
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+ C13 1uF VDDAY C18 C21 + C26 C28 0.1uF_N.M. VDDADC33 10uF + C30 0.1uF_N.M. VDDPGA33 1uF VDDQ 1uF VDDA33 10uF_N.M.
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8.3.1 CSP Package (PAC7301LT, no MIC)
VDDQ R1 300k VSSQ VDD_5V VDDQ 1uF C1 R5 1.5K C9 0.1uF L4 R18 0 DN R6 27 DP R8 27 DNC DPC L5 short C11 20p C12 20p short A' B' L3 short C10 USB5V JP1 1 2 3 4 5 HEADER 1X5 0.1uF
L1 VSSA
3.3uH
VDDAY
R17
0
VDDA
R2 0 RSTN 9 8 7 6
5
4
3
2 VDDADC33
VSSA_AUDIO
VDDMA5_AUDIO
VDDPGA33
VDDMIC28
RSTN
10 VDDMA5 11 VDDA33 12 13 14
MIC_N
GPO1
GPI3
1
U1
MIC_P VDDMA5 VDDA33 VSSQ GPI1
DP DN OSC_OUT VDDMD5 VSSQ EPR_EN
35 34 33 32 31 30 29 28 27
DP DN 10pF OSC_OUT Y1 R7 VDDMD5 10pF 1M C5 12MHz C18
A-A' (DN) and B-B'(DP)
OSC_OUT OSC_IN
PAC7301LT
15 VDDAY VDDAY M 16 17
VCOM EPR_DO/TR3 EPR_CS/TR1 EPR_SK/TR2 VDDAY VDDAY M
VSSA OSC_IN VDDQ
C3 C4 OSC_IN VDDQ C6
0.1uF VDDMA5 10uF +
EPR_DI/TR0
VSSAY
VDDD
VDDA
KEY
LED
1uF
VDDAY M
EPR_DI 18
EPR_SK 19
EPR_DO20
21
22
23
EPR_CS 24
25 LED
VDDA
VDDD
KEY
26
C7
1uF
VDDAY
U3
2 D1 LED-0603 C8 KEY VDD_5V 100k VDDMD5 VDDMA5 0 or 3.3uH R10 VDDQ 0 or 3.3uH R11 R19 1 R20 1k 1uF VDDA33
C13
1uF
VDDD
C14 R12 R13 R14 R15 10K_N.M. EPR_DO 10K_N.M. EPR_SK 10K_N.M. EPR_CS 10K_N.M. EPR_DI Open Open Open Open Open Open Open Short . . . Short Open Open Open . . . Short Short Short Open Short Short Short Short 2620 2621 (Def ault) C16
0.1uF VDDMD5 10uF +
PID IO_TRAP
R12 R13 R14 R15 PID
C15
1uF
VDDQ
2628 C17 262E 262F 1uF VDDA
PAC7301 PID IO_TRAP
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
21
PixArt Imaging Inc. E-mail: fae_service@PixArt.com.tw
V1.4 Nov 2007
PixArt Imaging Inc. PAC7301/PAC7302
8.3.2 CSP Package (PAC7302LT)
VDDQ
10pF
C3 Y1 R7 OSC_IN 1M C5 12MHz OSC_OUT R2 300k
L1 VSSA
3.3uH VSSQ
L2
3.3uH VSSA_Audio
10pF
1uF C1 VDDA 0 VDDMA5_AUD VDDPGA33 VDDMIC28 VDDADC33 R24 VDDAY
VSSQ
MIC_N
RSTN
DN
DP
R21 0
R25 0
0.1uF_N.M. C10 VDDMIC28 C11 22uF +
9
8
7
6
5
4
3
2 VDDADC33
VSSA_AUDIO
VDDMA5_AUDIO
VDDPGA33
VDDMIC28
MIC_N
RSTN
GPO1
GPI3
R9 R10 27 27 MIC_P 10 MIC_P VDDMA5 VDDA33 VSSQ GPI1 VDDMA5 11 VDDQ 1.5K R11 DP VDDA33 12 L3 short VDD_5V VDD5V C23 0.1uF C19 + 10uF L4 short R20 0 14 1 2 3 4 5 13
1
U1
C15 DP DN 35 34 33 32 31 C9 DP DN OSC_OUT VDDMD5 C22 C24 C16
0.1uF VDDMA5_AUD 10uF + 0.1uF VDDMA5 10uF +
OSC_OUT VDDMD5 VSSQ EPR_EN
PAC7301/7302LT
1uF
VDDAY M
30 29 C13 1uF VDDAY 28 27 OSC_IN VDDQ C18 C21 + 1uF VDDA33 10uF_N.M. 0.1uF_N.M. VDDADC33 10uF +
+5V + NC GND2
VCOM 9 8 VDDAY VDDAY M USBGND
15 16 17
VCOM EPR_DO/TR3 EPR_SK/TR2 VDDAY VDDAY M EPR_CS/TR1
VSSA OSC_IN VDDD VDDD 26 VDDQ
USBGND C29 R16 4.7nF/250V 10M
VSSAY
CON1 MINI USB 5P
EPR_DI/TR0
6 7
HC1 HC2
HC4 HC3
VDDA
KEY
EPR_DI 18
EPR_SK 19
EPR_DO20
21
22
23
EPR_CS 24
VDDMIC28
VDDA
KEY
25
LED
C26 C28
R23 5.1k VDD_5V R3 2.2k + C32 22uF C2 VDDMA5 X1 2.2uF R5 C4 R6 VCOM 10k 10k 2.2uF R8 2.2k R14 R15 10K_N.M. EPR_CS 10K_N.M. EPR_DI MIC_N MIC_P VDDMD5 0 or 3.3uH R18 0 or 3.3uH VDDMA5_AUD R17
U3
2 D1 LED-0603 KEY R26 100K
C30 R1 1k C31
0.1uF_N.M. VDDPGA33 10uF +
VDDQ
1
0 or 3.3uH R19
C8
1uF
VDDD
MICROPHONE R13 10K_N.M.
C6 C7
0.1uF 10uF +
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc. E-mail: fae_service@PixArt.com.tw
+ R12 10K_N.M. EPR_DO EPR_SK
PID IO_TRAP
R12 R13 R14 R15 PID 2620 2621 (Def ault) Open Open Open Open Open Open Open Short . . . Short Open Open Open . . . Short Short Short Open Short Short Short Short
C12 C14
0.1uF VDDMD5 10uF +
C17 C20
1uF
VDDQ 10uF_N.M.
2628 C25 262E C27 262F
1uF
+ VDDA 10uF_N.M. +
PAC7302 PID IO_TRAP
22
V1.4 Nov 2007
PixArt Imaging Inc. PAC7301/PAC7302
8.4 LGA Package (PAC7302LG)
VDDQ R2 R1 1k 1 LED-0603 L1 VSSA 3.3uH VSSQ 2 L2 3.3uH R22 0 VDDMIC28 R26 5.1k R3 0 R4 0 24 EPR_Enh 23 VDDD 22 VDDMD5 21 10pF C3 Y1 R7 OSC_IN 10pF 1M C5 12MHz DN DP 17 16 18 VDDQ 20 OSC_OUT 19 EPR_EnH VSSD VDDD VDDMD5 VDDQ OSC_OUT OSC_IN DN DP VDDAYM VDDMA5 VDDA33 VDDAY PAC7301/7302LG GPO1 VDDADC33 VSSA_AUDIO MIC_N MIC_P VDDMIC28 VCOM VDDPGA33 1 2 3 4 5 6 7 8 MIC_N MIC_P VDDMIC28 VCOM VDDPGA33 R6 10k 2.2uF R5 C4 10k 2.2uF R8 2.2k GPO1 VDDADC33 C2 X1 2.2k + C32 22uF MICROPHONE VDDA 0 C6 VDDMA59 C7 0.1uF C9 10uF + 1uF VDDAY M + GPI1 RSTN LED R28 100k 300k C1 1uF VDDMA5 VDDMD5 0 or 3.3uH R18 0 or 3.3uH R19 D1 VDDQ
VDD_5V
25
26
27
28
29 GPI1
VSSQ
VDDA
VSSA
DN
KEY
DP
RSTN
LED
NC
NC
30
U2
R27
VDDAY
VSSQ
15
14
13
VDDAYM12
VDDAY 11
R9 R10 27 27 KEY
VDDA33 10
VDDA
C13 U3 C10 VDDQ 1.5K R11 DP KEY VDD_5V L3 short L4 short C12 C14 1 2 3 4 5 C23 0.1uF C19 + 10uF 0.1uF VDDMD5 10uF C26 C17 9 8 C20 + 1uF VDDQ C22 6 7 USBGND C29 R16 4.7nF/250V 10M HC1 HC2 CON1 MINI USB 5P USBGND HC4 HC3 10uF_N.M. C24 VDDA 10uF_N.M. + 10uF C30 C31 + 0.1uF VDDMA5 C28 C8 1uF VDDD C11 22uF + C18 C21 0.1uF_N.M. VDDMIC28
1uF
VDDAY
1uF
VDDA33 10uF_N.M.
0.1uF_N.M. VDDADC33 10uF +
+
+
+5V + NC GND2
0.1uF_N.M. VDDPGA33 10uF +
C25 C27
1uF
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
23
PixArt Imaging Inc. E-mail: fae_service@PixArt.com.tw
V1.4 Nov 2007
PixArt Imaging Inc. PAC7301/PAC7302
9. Update History
Version V0.1 V0.2 V0.3 V0.4 V0.5 V0.6 V0.7 V0.8 V0.9 V1.0 V1.1 V1.2 V1.3 V1.4 Update Creation, Preliminary 1st version Added circuit/package information for 2nd version Changed circuit/package information for 3rd version Modified some string for 4th version Modified CSP package LC type for 5th version Modified MIC circuit for 6th version Modified MIC circuit for 7th version and changed CSP package LT type Support PAC7302PE/PM/LT/LG package. Write the Specifications TBD value LGA GPO1 replace GPI3, update PAC7301CS circuit GPO1/LED modified circuit for suspend, and update PAC7301/7302 circuit Update LGA/CSP package for marking code revision Modified reference circuit symbol. Added package sensor array dimension and update the newest package information. Only update reference circuit symbol. Date 11/24/2006 12/07/2006 12/25/2006 12/26/2006 12/26/2006 01/23/2007 01/29/2007 04/09/2007 05/02/2007 05/18/2007 06/29/2007 08/22/2007 08/28/2007 11/01/2007
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
24
PixArt Imaging Inc. E-mail: fae_service@PixArt.com.tw
V1.4 Nov 2007

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